home *** CD-ROM | disk | FTP | other *** search
/ SGI Origin & Onyx2 Patches 1998 May / Origin and Onyx2 System Disk Patches May 1998.img / dist / patchSG0002795.idb / usr / diags / IR / data / hip1b.qtcbist.z / hip1b.qtcbist
Text File  |  1998-03-05  |  2KB  |  42 lines
  1. tcbist_ram     1 core.pipe.in.icu.ram.dpr0
  2. tcbist_ram     2 core.pipe.in.icu.ram.dpr1
  3. tcbist_ram     3 core.pipe.in.gfx.ram.dpr0
  4. tcbist_ram     4 core.pipe.in.gfx.ram.dpr1
  5. tcbist_ram     5 core.pipe.in.gfx.ram.dpr2
  6. tcbist_ram     6 core.pipe.in.gfx.ram.dpr3
  7. tcbist_ram     7 core.pipe.in.gfx.ram.dpr4
  8. tcbist_ram     9 core.pipe.in.idma.fifo.ram.dpr0
  9. tcbist_ram     10 core.pipe.in.idma.fifo.ram.dpr1
  10. tcbist_ram     20 core.pipe.arm.sdram.tag.dpr0
  11. tcbist_ram     28 core.tbus.dma.odma.ram.dpr0
  12. tcbist_ram     29 core.tbus.dma.odma.ram.dpr1
  13. tcbist_ram     30 core.tbus.dma.odma.ram.dpr2
  14. tcbist_ram     31 core.tbus.dma.odma.ram.dpr3
  15. tcbist_ram     32 core.tbus.dma.odma.ram.dpr4
  16. tcbist_ram     33 core.tbus.dma.odma.ram.dpr5
  17. tcbist_ram     34 core.tbus.dma.odma.ram.dpr6
  18. tcbist_ram     35 core.tbus.dma.odma.ram.dpr7
  19. tcbist_hw_rst
  20. tcbist_sw_rst
  21. tcbist_ctrl    36:000000000000000000000000000000000000
  22. tcbist_sw_rst
  23. tcbist_ctrl    36:000000011100000000000000000000101001
  24. tcbist_poll1   0
  25. tcbist_sw_rst
  26. tcbist_ctrl    36:000000000001010000000000000000000000
  27. tcbist_sw_rst
  28. tcbist_comment forcing BIST failure
  29. tcbist_ctrl    36:000000000001010000000000000000110001
  30. tcbist_poll1   0
  31. tcbist_ctrl    36:000000000001010011000000000000101001
  32. tcbist_poll1   0
  33. tcbist_expect1 1 2 3 4 5 6 7 9 10 20 28 29 30 31 32 33 34 35
  34. tcbist_sw_rst
  35. tcbist_comment simple test - write followed by read of modulo-3 patt 0-5-A
  36. tcbist_ctrl    36:000000000001010000000000000000110001
  37. tcbist_poll1   0
  38. tcbist_ctrl    36:000000000001010000000000000000101001
  39. tcbist_poll1   0
  40. tcbist_expect0 1 2 3 4 5 6 7 9 10 20 28 29 30 31 32 33 34 35
  41. tcbist_ctrl    36:000000000011110000000000000000000000
  42.